There is known a technique of operating, at the same power supply voltage, a MOS (Metal Oxide Semiconductor) type field effect transistor group having different thicknesses of gate insulating films, different threshold voltages which are controlled by impurity concentration in a channel region directly under the gate insulating film, and different off currents, by using the transistor group for an internal circuit and a power supply protection circuit.
Further, for the MOS type field effect transistor, there is known a technique of controlling the threshold voltage by forming the channel region to be non-doped or to have a very low impurity concentration and providing an impurity region having a higher concentration than the channel region, under such a channel region. This technique is expected as a technique of suppressing the variation of the threshold voltage and achieving power supply voltage reduction and power consumption reduction.
See, for example, Japanese Laid-open Patent Publication Nos. 2004-39775 and No. 2014-72512.
Meanwhile, the off current of a transistor includes the sum of sub-threshold leak current and junction leak current.
In a transistor having an impurity region of a higher concentration than the impurity concentration of the channel region, provided under the channel region, the threshold voltage is controlled by the adjustment of the concentration of the higher concentration impurity region. In this case, since the sub-threshold leak current and the junction leak current change according to the concentration of the impurity region, there is a possibility that resultantly the off current including the sum of the both leak currents is not suppressed low. It is preferable to reduce the off current from the viewpoint of the power consumption reduction.